/* ***** BEGIN LICENSE BLOCK ***** 
 * Version: RCSL 1.0/RPSL 1.0 
 *  
 * Portions Copyright (c) 1995-2002 RealNetworks, Inc. All Rights Reserved. 
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 * The contents of this file, and the files included with this file, are 
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 * Version 1.0 (the "RPSL") available at 
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 * the file under the RealNetworks Community Source License Version 1.0 
 * (the "RCSL") available at http://www.helixcommunity.org/content/rcsl, 
 * in which case the RCSL will apply. You may also obtain the license terms 
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 * applicable to this file, the RCSL.  Please see the applicable RPSL or 
 * RCSL for the rights, obligations and limitations governing use of the 
 * contents of the file.  
 *  
 * This file is part of the Helix DNA Technology. RealNetworks is the 
 * developer of the Original Code and owns the copyrights in the portions 
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 * This file, and the files included with this file, is distributed and made 
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 * 
 * Technology Compatibility Kit Test Suite(s) Location: 
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 * Contributor(s): 
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 * ***** END LICENSE BLOCK ***** */ 

#ifndef _CPUIDENT_H_
#define _CPUIDENT_H_

#ifdef __cplusplus
extern "C" {
#endif

/*
 * CPU architectures. Currently, only Intel architectures (x86) and ARM are
 * detected by this code.
 */

typedef enum
{
    ulArchitectureUNKNOWN = 0,
    ulArchitectureIntel   = 1,
    ulArchitectureARM_ARCH2 = 2,
    ulArchitectureARM_ARCH3 = 3,
    ulArchitectureARM_ARCH4 = 4,
    ulArchitectureARM_ARCH4T= 5,
    ulArchitectureARM_ARCH5 = 6,
    ulArchitectureARM_ARCH5T= 7,
    ulArchitectureARM_ARCH5TE=8
} CPUArchitecture;

/*
 * Intel Architecture processor families.
 * Do not change these values -- they match with the results of the cpuid()
 * instruction.
 * Refer to Intel document number 24319202, section 8.1.3.
 */

typedef enum
{
    ulFamilyUNKNOWN     =  0,
    ulFamily80386       =  3,
    ulFamily80486       =  4,
    ulFamilyPENTIUM     =  5,
    ulFamilyPENTIUM_PRO =  6,
    ulFamilyP4          =  15
} IntelCPUFamily;

/*
 * ARM architecture families
 */

typedef enum
{
    ulFamily_PREARM7 = ulFamilyUNKNOWN + 1,
    ulFamily_ARM7,
    ulFamily_POSTARM7
} ARMCPUFamily;

/*
 * Intel architecture specific features
 */
typedef struct
{
    IntelCPUFamily family ;
    int model ;
    int stepping ;

    int hasMMX; /* MMX instructions available? */
    int hasMSR; /* model specific registers (Pentium) available? */
    int hasTSC; /* rdtsc / Time stamp counter available? */
    int hasPMC; /* rdpmc / Performance monitoring counter available? */
    int hasSSE; /* Katmai new instructions (SSE) available? */
    int hasSSE_OSSupport; /* OS support for SSE floating point available? */
    int hasSSE2; /* SSE2 instructions available? */
} IntelCPUInformation ;

typedef struct
{
    int family ;
    //    int architecture ;
    int implementor ;
    char description[128] ;

    // only valid if family >= ARM7
    int variant ;
    int primaryPartNo ;
    int revision ;

    union
    {
        struct {
            int coreGeneration ;
            int coreRevision ;
            int productNumber ;
	} XScale ;
    } specific ;
} ARMCPUInformation ;

/*
 * ARM Implementors
 */

enum {
    ARM_IMPL_UNKNOWN = 0x00,
    ARM_IMPL_ARM     = 0x41, /* 'A' */
    ARM_IMPL_DEC     = 0x44, /* 'D' */
    ARM_IMPL_Intel   = 0x69  /* 'i' */
} ;

/*
 * CPUInformation
 */

typedef struct
{
    CPUArchitecture architecture ;
    union
    {
        IntelCPUInformation m_x86 ;
        ARMCPUInformation m_arm ;
    } specific ;
} CPUInformation ;

extern void CPUIdentify(CPUInformation* pInfo) ;

#ifdef __cplusplus
} // extern "C" {}
#endif

#endif /* _CPUIDENT_H_ */
